1. Field of the Invention
The present invention relates to a semiconductor device containing a via and a method of forming a via in a semiconductor device.
2. Discussion of the Background
During the semiconductor fabrication process multiple conductive layers such as metal or polysilicon are often deposited on a semiconductor substrate. Conductive layers are sometimes separated from each other by an insulating dielectric layer, such as silicon dioxide. These conductive layers are often selectively connected or "wired" together in order to allow for conduction of electricity in a desired pattern. One means of connecting conductive layers is through the formation of a via, which is a channel or plug of conductive material typically formed between layers of conductive materials.
A via may be formed by etching a channel in an insulating layer separating two conductive material layers and filling the channel with a conductive material.
During the formation of a via, a problem sometimes arises from high contact resistance at the bottom of the via, between the via material and the region of the conductive layer to which it contacts. In order to provide for a low contact resistance at the bottom of a via, it has been conventional to form thick layers of Ti (typically about 500-1,400 .ANG. thick) by physical deposition methods such as sputtering. A thick layer has been used to ensure good contact between the Ti and the conductive region at the bottom of the via. (See for example Wolf Silicon Processing for the VLSI ERA, v2, pp 247-248 or U.S. Pat. No. 5,399,530).
In order to promote adherence of a via material to the Ti layer, it has also been known to use a glue layer as a transition between the titanium and the via material.
However, when a via having a high aspect ratio (height/width, or step height/step-step spacing) is used, it can be difficult to deposit a thick Ti layer and/or a glue layer into the via hole. These difficulties sometimes produce uneven deposition of materials in the via (i.e. cusping, voids, etc). It is also generally more difficult to completely avoid particulate impurities in vias having relatively high aspect ratios. Therefore, the electrical properties of such a high aspect ratio via can vary unpredictably resulting in uncontrolled changes in the resistivity. This is especially true at high aspect ratios, since the resistivity of the via may change in a manner depend ant on the aspect ratio of the via. The problem of filling small, high aspect ratio contact holes has been discussed by Singer in Semiconductor International, August 1994, p 57, "The Interconnect Challenge: Filling Small, High Aspect Ratio Contact Holes". Thus, a via-forming method that provides an aspect ratio-independent resistivity is valuable.
The present inventors have discovered that, contrary to conventional practice, a thin liner layer may be used in a high aspect ratio via, while still obtaining a low contact resistance between the via and the underlying material.